Cache Emulator for SMP Systems
Authors: Ivan Šimeček

Cache emulator, cache model, symmetric multiprocessing.


     Every modern CPU use a complex memory hierarchy, which consists of levels of cache memories. It is really difficult to predict the behavior of this hierarchy for the given program. The situation is even worse in SMP (symmetric multiprocessing) systems. The Cache emulator (shortly CE) can simulates the behavior of caches inside SMP system and compute the number of cache misses during a computation. All measurements are done in the "off-line" mode on the one CPU; the CE uses own virtual cache memory for the exact simulation. It also means that another CPU activity doesn't influence the behavior of the CE. 


final version (in .DOC format)

BibTex entry:
  author =       "I. \v{S}ime\v{c}ek",
  title =        "Cache Emulator for SMP Systems",
  journal =      "CTU Workshop",
  pages =        "114-115",
  month =        feb,
  year =         "2006",
  isbn =         "80-01-03439-9",
  Address =      "Prague, Czech Republic"