In this paper, we describe a probabilistic model for estimation of the numbers of cache misses during the sparse matrix-vector multiplication (for both general and symmetric matrices) and the Conjugate Gradient algorithm for 3 types of data caches: direct mapped, s-way set associative with random or with LRU replacement strategies. Using HW cache monitoring tools, we compare the predicted number of cache misses with real numbers on Intel x86 architecture with L1 and L2 caches. The accuracy of our analytical model is around 96%.