ČVUT WORKSHOP'05

Software Cache Analyzer 
Authors: Ivan Šimeček and Pavel Tvrdík
Keywords

High-performance,  processor architecture, cache hierarchy, cache miss analyzer.


Abstract

Every modern CPU use a complex memory hierarchy, which consists of levels of cache memories. It is really difficult to predict the behavior of this hierarchy for the given program. The Cache Analyzer (shortly CA) simulates the behavior of a real microprocessor’s cache and compute the number of cache misses during a computation. All measurements are done in the "off-line" mode; the CA uses own virtual cache memory for the exact simulation. It also means that another CPU activity doesn’t influence the behavior of the CA. 

The cache model we consider corresponds to the structure of L1 - L3 caches on vast of modern memory architectures.


Download:
final version (in .DOC format)

BibTex entry:
@inproceedings{JA_WOR_CACHE,
  author =       "P. Tvrd\'{\i}k and I. \v{S}ime\v{c}ek",
  title =        "Software Cache Analyzer",
  journal =      "CTU Workshop",
  volume =       "9",
  pages =        "180-181",
  month =        mar,
  year =         "2005",
  isbn =         "80-01-03201-9",
  Address =      "Prague, Czech Republic"
}

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