Personal research page
  author: Ivan Šimeček  (xsimecek at fel dot cvut dot cz)
address: Department of Computer Science, Faculty of Electrical Engineering, Czech Technical University, Technická 2, 166 27 Prague 6, Czech Republic


Keywords

High-performance, numerical linear algebra, cache memory, cache behavior models, code restructuring, architecture dependent optimization, dynamical loop reversal, loop blocking, loop unrolling, loop unrolling-and-jam.


Research papers



2009
Acta Polytechnica: Memory Hierarchy Behavior Study during the Execution of Recursive Linear Algebra Library

Acta Polytechnica: The acceleration of the sparse matrix-vector multiplication by the region traversal

2008
PhD thesis: Architecture-Dependent Linear Code Optimizations

MEMICS'08: Sparse Matrix-Vector Multiplication - Final Solution?

SNA'08: Sparse Matrix Computations with Quadtrees

SNA'08: CPU or GPU: that is the question

ČVUT WORKSHOP'08: CPU or GPU: that is the question

ČVUT WORKSHOP'08: An Overview of Factorization of Large Integers Using the GMP Library

ČVUT WORKSHOP'08: Comparison of Different Implementations of BLAS and LAPACK Libraries with Application in Computational Fluid Dynamics

ČVUT WORKSHOP'08: Sparse Matrix Computations with Quadtrees

2007
PPAM'07: Sparse Matrix-Vector Multiplication - Final Solution?

SNA'07: A New Format for sparse Matrix-vector Multiplication

SNA'07: Recursive implementation of high performance numerical algebra library

ČVUT WORKSHOP'07: Cache Misses Prediction by Means of Data Mining Methods

ČVUT WORKSHOP'07: A New Format for the Sparse Matrix-vector Multiplication

ČVUT WORKSHOP'07: An Adaptive Solver for Fluid Dynamics on the GPU

ČVUT WORKSHOP'07: A New Approach for Accelerating the Sparse Matrix-vector Multiplication

2006
Acta Polytechnica: A simple cache emulator for evaluating cache behavior for SMP systems

Acta Polytechnica: Performance aspects of sparse matrix-vector multiplication

SYNASC'06: A New Approach for Accelerating the Sparse Matrix-vector Multiplication

SNA'06: Cache adaptive blocking format

ČVUT WORKSHOP'06: Analytical modelling of linear codes

ČVUT WORKSHOP'06: Cache Misses Analysis by Means of Data Mining Methods

ČVUT WORKSHOP'06: Cache Emulator for SMP Systems

ČVUT WORKSHOP'06: Optimization of SESOL Package

ČVUT WORKSHOP'06: Recursive Implementation of High Performance Numerical Algebra Library

ČVUT WORKSHOP'06: A New Diagonal Blocking Format and Model of Cache Behavior for Sparse Matrices

2005
PPAM'05: A New Diagonal Blocking Format and Model of Cache Behavior for Sparse Matrices

SNA'05: Optimalizace a hodnocení efektivity lineárních kódů

Documenta Geonica'05: Computer-related aspects of mathematical modelling at the Institute of Geonics

ČVUT WORKSHOP'05: Software Cache Analyzer

ČVUT WORKSHOP'05: Possibilities of GPU Computing

ČVUT WORKSHOP'05: Architecture Dependent Linear Code Optimizations

ČVUT WORKSHOP'05: Semi-sparse Cholesky Factorization

2004
HPSEC'04: Analytical Model for Analysis of Cache Behavior during Cholesky Factorization and Its Variants

NAA'04: Performance optimization and evaluation for linear codes

ČVUT POSTER'04: Improving of the performance of sparse matrix-vector multiplication on the modern architectures

2003
PPAM'03: Analytical Modeling of Optimized Sparse Linear Code

2001
Diploma thesis: Parallel matrix-matrix multiplication



Projects


The Cache Analyzer

Cache Emulator for SMP Systems

High Performance Recursive Linear Algebra Library

Quad-tree sparse matrix library




Curricula vitae


Degrees and titles. (all from CTU in Prague)
Engineer in Computer Science (1999)

Employment and visiting positions.
Sep 1999 -- Sep 2004   PhD student, Department of Computer Science FEE CTU, Prague
Oct 2004 --                   Assistant Professor, Department of Computer Science FEE CTU, Prague



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