Poster ČVUT 2004

Improving of the performance of sparse matrix-vector multiplication on the modern architectures
Author: Ivan Šimeček
Keywords

Sparse matrix-vector multiplication, high-performance,  cache locality, sw-pipelining, loop unrolling, loop fusion.


Abstract

In this paper, we describe source code transformations based on sw-pipelining, loop unrolling, and loop fusion for the sparse matrix-vector multiplication that enable data prefetching and overlapping of load and FPU arithmetic instructions and improve the temporal cache locality. The paper represents evaluation of results of these optimizations on various HW platforms.


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BibTex entry:
@inproceedings{JA_POSTER,
  author =       "I. \v{S}ime\v{c}ek",
  title =        "Improving of the performance of sparse matrix-vector multiplication on the modern architectures",
  journal =      "CTU FEE POSTER",
  volume =       "9",
  pages =        "182-183",
  month =        mar,
  year =         "2005",
  isbn =         "80-01-03201-9",
  Address =      "Prague, Czech Republic"
}

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