Cache Emulator for SMP Systems
Author: Ivan Šimeček
Keywords
Cache emulator, cache model, symmetric multiprocessing.
Abstract
Every
modern CPU use a complex memory hierarchy, which consists of levels of
cache memories. It is really difficult to predict the behavior of this
hierarchy for the given program. The situation is even worse in SMP
(symmetric multiprocessing) systems. The Cache emulator (shortly CE)
can simulates the behavior of caches inside SMP system and compute the
number of cache misses during a computation. All measurements are done
in the "off-line" mode on the one CPU; the CE uses own virtual cache
memory for the exact simulation. It also means that another CPU
activity doesn't influence the behavior of the CE.
Overview of the CE in Proceedings of CTU WORKSHOP, 2006
What's new
March 22 2006 - version 0.95 of the CE is released.
History
version 0.95 - some bugs removed
Known bugs
- The CE can be use also for estimation of the TLB misses. Since TLB is usually implemented
as fully-associative, searching in the CA is very difficult and it slows down the computation.
- I have not verified the 64bit version of the CE.
(Possible) future works
- Put the CE onto SOURCEFORGE (almost done).
- Add a support for exclusive levels of caches.
- Speedup the execution (if it is possible).
- Implement also another coherency policies than MESI.
- Add a support for OpenMP primitives.
Used in papers
Cache Emulator for SMP Systems
Download:
Cache Emulator for SMP 0.95 Cache
Emulator for SMP
0.95
Example of using the CE Gemm SMP
Cache parameters definition files
(please download from the CA project)
Number of cores is specified by #define
MAX_PROC 4 statement.
