Author: Ivan Šimeček
Processor architecture, cache hierarchy, software cache emulation, cache miss analyzer.
Every modern CPU use a complex
memory hierarchy, which consists of levels of cache memories. It is
difficult to predict the behavior of this hierarchy for the given
program. The Cache Analyzer (shortly CA) simulates the behavior of
a real microprocessor’s cache and compute the number of cache misses
computation. All measurements are done in the "off-line" mode; the CA
uses own virtual cache memory for the exact simulation. It also means
another CPU activity doesn’t influence the behavior of the CA. The
cache model we
consider corresponds to the structure of L1 - L3 caches on vast of
Overview of the CA in Proceedings of CTU WORKSHOP, 2005
March 29 2005 - version 1.02 of the CA is released.
March 21 2005 - version 1.01 of the CA is released.
March 14 2005 - version 1.0 of the CA is released.
March 9 2005 - version 0.99 of the CA is
version 1.02 - some minor functions are added.
version 0.99 - the CA is corrected and its speed is slightly
version 0.9 - the CA is completely rewritten to be easy to use and more
version 0.5 - the first fully functional version of the CA.
- The CA can be use also for estimation of the TLB misses. Since TLB is usually implemented
as fully-associative, searching in the CA is very difficult and it slows down the computation.
- I have not verified the 64bit version of the CA.
(Possible) future works
- Put the CA onto SOURCEFORGE (almost done).
- Add a support for exclusive levels of caches.
- Speedup the execution (if it is possible).
Used in papers
Almost in all of my papers (expect these focused on SMP or GPGPU).
Cache Analyzer 1.02 Cache Analyzer
Cache Analyzer 1.01 Cache Analyzer
Cache Analyzer 1.00 Cache Analyzer
Cache Analyzer 0.99 Cache Analyzer
Cache Analyzer 0.50 Cache Analyzer 0.5
Example of using the CA Gemm SMP
Cache parameters definition files: