Software Cache Analyzer

Author: Ivan Šimeček

Processor architecture, cache hierarchy, software cache emulation, cache miss analyzer.

Every modern CPU use a complex memory hierarchy, which consists of levels of cache memories. It is really difficult to predict the behavior of this hierarchy for the given program. The Cache Analyzer (shortly CA) simulates the behavior of a real microprocessor’s cache and compute the number of cache misses during a computation. All measurements are done in the "off-line" mode; the CA uses own virtual cache memory for the exact simulation. It also means that another CPU activity doesn’t influence the behavior of the CA. The cache model we consider corresponds to the structure of L1 - L3 caches on vast of modern memory architectures.

Overview of the CA in Proceedings of  CTU WORKSHOP, 2005

What's new
March 29 2005 -  version 1.02 of the CA is released.
March 21 2005 -  version 1.01 of the CA is released.
March 14 2005 -  version 1.0 of the CA is released.
March 9 2005   -  version 0.99 of the CA is released. 
version 1.02 - some minor functions are added.
version 0.99 - the CA is corrected and its speed is slightly improved.
version 0.9 - the CA is completely rewritten to be easy to use and more pure.
version 0.5 - the first fully functional version of the CA.

Known bugs

(Possible) future works

Used in papers
Almost in all of my papers (expect these focused on SMP or GPGPU).
Cache Analyzer 1.02 Cache Analyzer 1.02
Cache Analyzer 1.01 Cache Analyzer 1.01
Cache Analyzer 1.00 Cache Analyzer 1.0
Cache Analyzer 0.99 Cache Analyzer 0.99
Cache Analyzer 0.50 Cache Analyzer 0.5

Example of using the CA Gemm SMP

Cache parameters definition files:

Core name
L2 Size
Corresponding file
Pentium 3 Katmai 256 KB p3kat256.def
Pentium 3 Katmai 512 KB
Pentium 4 Celeron 128 KB
Pentium 4 Willamette 256 KB
Pentium 4 Northwood 512 KB
Itanium Merced 2 M
Itanium Merced 4 M
Itanium 2 McKinley 1.5 M
Itanium 2 McKinley 3 M