Acta Polytechnica

A simple cache emulator for evaluating cache behavior for SMP systems

Author: Ivan Šimeček

Cache hierarchy, cache emulator, symmetric multiprocessing, MESI .


Every modern CPU uses a complex memory hierarchy, which consists of multiple cache memory levels. It is very difficult to predict the behavior of this hierarchy for a given program (for details see [1, 2]). The situation is even worse for systems with a shared memory. The most important example is the case of SMP (symmetric multiprocessing) systems [3]. The importance of these systems is growing due to the multi-core feature of the newest CPUs. The Cache Emulator (CE) can simulate the behavior of caches inside an SMP system and compute the number of cache misses during a computation. All measurements are done in the "off-line" mode on a single CPU. The CE uses its own emulated cache memory for an exact simulation. This means that no other CPU activity influences the behavior of the CE. This work extends the Cache Analyzer introduced in [4].

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BibTex entry:
@ARTICLE{JA_ACTA, author = {Ivan \v{S}ime\v{c}ek},
title = {A simple cache emulator for evaluating cache behavior for SMP systems},
journal = {Acta Polytechnica},
year = {2006},
volume = {46},
pages = {47-49},
number = {2},
month = {June},
issn = {1210-2709}